1. Field of the Invention
The present invention relates to semiconductor switches, particularly to the field effect transistor (FET) type, which are based upon the Mott metal-insulator phenomenon.
2. Brief Description of the Prior Art
Existing computer circuits, both logic and dynamic random memory (DRAM) are dominated by field effect transistors (FET). FETs have been more widely used lately. Of these, the metal oxide field effect semiconductors MOSFETS (metal oxide semiconductor field effect transistors) have been the leading choice of designers. In this type of transistor, a conducting channel of either electrons or holes is established between two regions, called xe2x80x9csourcexe2x80x9d and xe2x80x9cdrainxe2x80x9d to which ohmic low resistance contacts are made. Control of the xe2x80x9csourcexe2x80x9d current to the xe2x80x9cdrainxe2x80x9d current is achieved by applying a potential to the gate electrode, which affects the width of the conducting channel and/or the number of mobile carriers in the channel. Power gain is achieved between the gate source input terminal and the drain source output because of the high input impedance.
A bipolar junction transistor is formed using three doped semiconductor regions separated by two PN junctions. The device is called a bipolar junction transistor (BJT) because the current flow involves carriers of both polarities (holes and electrons). A BJT can be fabricated either as a PNP transistor or a NPN transistor. The central region is called the base. One of the junctions is forward-biased and is called the emitter-base junction. The other junction is reverse biased and is called the collector-base junction. The three terminals are referred to as emitter, base and collector terminals. The regions are doped either lightly or heavily depending upon the use to which the BJT is to be put.
The FET has an extremely high input impedance as noted above, and has a better frequency response than the BJT. The small signal gain of a FET is not as high as that of a BJT; however the FET is a good alternative to the BJT in those areas of application where high impedance and a better frequency response is required. FETs can also be used as constant current sources and voltage controlled resistors in certain special applications. The important areas of use of FETs are digital circuits and systems.
In general, the basic structure of a FET has a main body which is a single continuous length of N-type semiconductor material. However, there is a small section of P-type material placed on either side of the main N-type section. Both of these P-type sections are connected together electrically. The lead connected to these sections is the gate. The other two leads (source and drain) are connected to either end of the N-type material piece.
The semiconductor channel is backed by a substrate of the opposite type of semiconductor. For example, if the channel is made up of an N-type semiconductor, a P-type semiconductor is used as the substrate. MOSFETs are also characterized as depletion or enhancement mode FETs. Depletion mode FETs reduce the current flow by increasing the negative voltage applied to the gate (assuming an N-type channel). In enhancement mode FETs, assuming an N-channel device, a positive voltage is applied between the gate and the source. The higher the value of the voltage, the greater the number of holes drawn from the N-type source into the P-type substrate. These holes then traverse into the N-type region, drawn by the voltage applied between the drain and the source. Thus increasing the voltage on the gate, results in an increase in the channel current (i.e., the current from source to the drain).
The MOSFET is approaching the intrinsic physical limits in channel length, due to, inter alia, doping and double depletion effects. Thus the exponential increase in circuit density on a chip predicted by Moore""s Law is not expected to be maintained by Si based devices. The concept of exploiting the Mott metal-insulator transition to make a FET-like switching device which allows functionality for channel lengths on the scale of 10 nm is known. The approach used herein is to replace the silicon channel by a layer of Mott insulator material. The present invention relates to a FET using oxide materials said FET operating at room temperature.
A non Si-based structure similar to that of the present invention has been explored in the literature in the work on xe2x80x9cSuperconducting FETxe2x80x9d (SuFETS) such as are described in J. Mannhart, J. G. Bednorz, K. Muller and D. G. Schlom, Z. Phys. 13 Condensed Matter, 83, 307 (1991); A. Levy, J. P. Falck, M. A. Kastner and R. J. Birgeneau, Phys. Rev. B 51, 648 (1995); E. H. Taheri, J. W. Cochrane and G. J. Russell, J Appl. Phys., 77 761, (1995); J. Mannhart, Supercond. Sci. Technol. 9, 49, (1996) and references cited in each, the contents of which are all incorporated by reference herein.
The typical SuFET device comprises a channel of superconducting material, (such as fully oxygenated YBCO in the superconducting state) with source and drain contacts on the superconducting material, a gate insulator (such as strontium nitrate) and a gate electrode. In the most common implementation of the SUFET as disclosed in the references noted above, the device is operated near the superconducting transition temperature and a gate field is applied to induce a transition from a superconducting state to an insulating state. A fundamental difficulty with such SUFET devices is the extremely short electric field screening length of superconducting materials which limits the ability of the gate field to modulate the bulk of the channel.
There have also been attempts (e.g., See Taheri, et al. above) to induce superconductivity in an initially insulating channel by applying a gate electric field. This approach is difficult because of the extremely high fields needed to induce a sufficient density of carriers in the channel to undergo insulator superconductor transition. It must be kept in mind however, that this work has been aimed entirely on attempts to take a device with a channel which can undergo a transition between superconducting and insulating states in the channel, and therefore it must be operated at a temperature near the superconducting transition temperature. The present invention is distinct in that a metal insulator transition is utilized in oxide materials to make a device which can operate at room temperature, without the need for the superconducting state.
To more specifically describe the typical prior art enhancement mode FET that uses an oxide channel, reference is made to FIG. 1. Enhancement mode oxide channel FET 100 has a source electrode 101, drain electrode 102, gate electrode 103, gate insulator 104 and channel 105.
It is well known that copper compounds, specifically, cuprates, form a class of materials which demonstrate Mott metal insulator transition. This property makes cuprates suitable for use as the molecular layer in the transistor. In addition, cuprates are well suited for integration with high dielectric oxides such as strontium titanate (SrTiO3) and (Ba1xe2x88x92x, Srx, TiO3), which are all materials suitable as the material used to comprise gate insulator 104.
In cuprate conductors, the conduction band is formed from well-defined atomic or molecular orbitals. In a cuprate semiconductor for example, this role is the result of dx2-y2 symmetry orbitals on the Cu sites. In another example, KnC60, the threefold degenerate set of lowest unoccupied molecular orbitals (LUMO) of C60 play an analogous role. The simplest model to describe such materials is the Hubbard model described by J. Hubbard, in Proc. Roy. Sci. (London) A276, 238(1963); A277, 237(1963); A281, 401(1963) which are incorporated by reference herein.
In an essentially ordered system, such as a cuprate CuO2 plane, there are found to be two possible global states of the system: insulator and metal. These states are separated by the Mott Transition as described by N. Mott in Metal Insulator Transitions, Taylor and Francis, London, 1990 which is hereby incorporated by reference herein. Further descriptions of atomic and molecular structures and the method of operation are found in copending cases Y0996-069 and Y0997-297.
A method found in the prior art for preparing the device found in FIG. 1 was to grow it on a niobium-doped strontium titanate (Nbxe2x80x94SrTiO3) substrate 106. Niobium doping makes substrate 103 conducting. Substrate 103 is the gate electrode in device 100. A dielectric spacing layer 104, approximately 1800 Angstroms thick was grown epitaxially on substrate 106 by the standard self assembly process of laser ablation single crystal deposition of strontium titanate in a vacuum deposition chamber. It has been determined that in order to obtain good dielectric properties for gate insulator spacing layer 104, (e.g., high breakdown voltage), low leakage and high dielectric constant, deposition must take place in the presence of oxygen. A typical example of same using device 100 would utilize an oxygen pressure of approximately 300 milliTorr. Without removing the device from the laser ablation vacuum deposition chamber, approximately 200 Angstroms thick Mott transition layer channel 105 consisting of cuprate Y0.5Pr0.5Ba2Cu3O7-8 was epitaxially grown on gate insulator 104 with the standard self-assembly process of laser ablation single crystal deposition with partial oxygen pressure (approximately 4 milliTorr) above the device. This enables control of the stoichiometry of Mott transition layer 105, yielding desirable properties, including sheet resistance. Source and drain electrodes were then deposited on top of cuprate Mott transition layer by electron beam evaporation through a contact mask. Source and drain electrodes are typically platinum 50 micronsxc3x9750 microns, with a thickness of about 2000 Angstroms. Device 100 has a channel length of about 5 microns and a channel width of about 50 microns. The large ratio of the area of the source and drain electrodes compared with the thickness of the cuprate layer allows the electrical conduction to the cuprate Mott transition layer which is at the cuprate/titanate interface.
The present invention relates to an oxide based, dual gate room temperature transistor device. The first embodiment of the present invention is to form a transistor device which is capable of improved switching between two states of high and low conductivity upon simultaneous application of a suitable gate voltage to both gates. The invention is capable of working in both an enhancement mode and a depletion mode. In particular, the invention relates to field effect transistors (FET) in which the channel of same is made from materials characterized by an electrical conductivity which can undergo an insulator-metal transition (i.e. Mott transition) upon application of an electric field. The device of the present invention uses a channel comprising such a Mott material, in which charge carriers, either holes or electrons, are strongly correlated. The Mott transition determines the metal-insulator switching and has been shown to be controlled by an external gate electrode. (See e.g., xe2x80x9cA Field Effect Transistor Based On The Mott Transition In A Molecular Layer,xe2x80x9d Zhou, et al. Appl. Phys. Lett. 70 (5) p.598, (1997); xe2x80x9cMott Transition Field Effect Transistor,xe2x80x9d Newns, et al., Appl. Phys. Lett. 73 (6) p.780, (1998), the contents of which are hereby incorporated by reference herein.)
In the oxide based transistors of the present invention, the ideal situation occurs when the channel layer possesses a high degree of long-range order arising from layer by layer epitaxial growth where there is perfect lattice formation between the substrate and the layer being grown. Such an ideal situation, however, results in strong electric-field screening properties of the transistor channels when in the metallic state. According to the theory of Mott-FET transistors, in, for example an enhancement mode architecture, the change in conductivity occurs mainly in a few atomic layers in the channel material. These are the channel layers that are exposed to the highest absolute value of electrical field inside the material upon application of the gate voltage. By construction, these layers are closest to the interface with the gate insulator. As these layers become conducting they screen the electric field efficiently creating a discontinuity that leaves the other layers in the insulating state. The use of dual gate architecture allows the use of both interfaces therefore improving the performance of the device. It also allows one to obtain the same value of gate conductivity as a single gate device but with a lower absolute value of the applied voltage.
Conversely, in the case of a depletion mode device, the channel in the zero gate field state is highly conducting and therefore capable of efficiently screening the gate electric field. The use of dual gate architecture makes gate electric field modulation of the entire channel more facile therefore improving the performance of the device. It also allows one to obtain the same value of gate conductivity as a single gate device but with a lower absolute value of the applied voltage.
A second embodiment of the present invention is to form a transistor device which is capable of switching between up to four states of different conductivity upon application of sequential voltages to the gates.
The distinctions between the two embodiments are clarified by the following tables. The conductivity possibilities arising applying electric field E1 to gate 1 and E2 to gate 2 in the dual gate device are as follows:
wherein the magnitude of the conductivity obeys the general rule: xe2x88x92|3, (3xe2x80x2)| greater than |2, (2xe2x80x2)| greater than |1, (1xe2x80x2)| greater than |0, (0xe2x80x2)|xe2x80x94. These possible states of conductivity can be achieved with a single voltage source using different voltage levels. These states can also be obtained by making the two oxides of the same material, but constructed of a different thickness; or by making the two oxides of different material but the same thickness or different material and different thickness. In that case the following conductivity states are obtained:
The first embodiment occurs in the case when both gates are connected to the same voltage source. Then the result is a two state device (0 and 3) or (3xe2x80x2 and 0xe2x80x2) with an enhanced conductivity ratio compared to a single gate device. The second embodiment occurs when voltages are applied sequentially to the two gates resulting in the four state devices shown in the tables.
The various features of novelty which characterize the invention are pointed out with particularity in the claims annexed and forming a part of the disclosure. For a better understanding of the invention, its operating advantages, and specific objects attained by its use, reference should be had to the drawing and descriptive matter in which there are illustrated and described preferred embodiments of the invention.